prga.core.context module¶
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class
prga.core.context.
Context
(template_search_paths=None, **kwargs)¶ Bases:
prga.util.Object
The main interface to PRGA architecture description.
Parameters: template_search_paths ( str
orContainer
[str
]) – Additional search paths other than the default onesKeyword Arguments: **kwargs – Custom attributes assigned to the context Architecture context manages all resources created/added to the FPGA, including all modules, the routing graph, programming circuitry and more.
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_add_module
(module)¶ Add
module
into the database of this context.Parameters: module ( Module
) –Returns: Return type: Module
-
_database
¶
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_fasm_delegate
¶
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_globals
¶
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_prog_entry
¶
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_renderer
¶
-
_segments
¶
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_switch_delegate
¶
-
_top
¶
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_tunnels
¶
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_verilog_headers
¶
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add_verilog_header
(f, template, *deps, key=None, **parameters)¶ Add a Verilog header. This rendering task will be collected via the
VerilogCollection
pass.Parameters: - f (
str
) – Name of the output file - template (
str
) – Name of the template or source file - *deps (
str
) – Other header files that this one depends on
Keyword Arguments: - key (
str
) – A key to index this verilog header. Default tof
- **parameters – Extra parameters for the template
- f (
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build_array
(name, width=1, height=1, *, set_as_top=None, edge=None, **kwargs)¶ Create an array in abstract view.
Parameters: - name (
str
) – Name of the array - width (
int
) – Width of the array - height (
int
) – Height of the array
Keyword Arguments: - set_as_top (
bool
) – By default, the first array created is set as the top-level array. If this is not intended, set this boolean value explicitly - edge (
OrientationTuple
[bool
]) – Specify on which edges of the top-level is the array. This affects where IO blocks can be instantiated, and how some switch boxes are created - **kwargs – Additional attributes to be associated with the array. Beware that these
attributes are NOT carried over to the design view automatically generated by
Translation
Returns: Return type: - name (
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build_design_view_primitive
(name, *, key=None, not_cell=False, **kwargs)¶ Create a primitive in design view.
Parameters: name (
str
) – Name of the design-view primitiveKeyword Arguments: - key (
Hashable
) – Key of the created module in the database. Same asname
if not set, or same as the abstract view if the abstract view already exists - not_cell (
bool
) – If set, the design-view primitive is not a cell module - **kwargs – Additional attributes to be associated with the primitive
Returns: Return type: - key (
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build_io_block
(name, *, input_only=False, output_only=False, **kwargs)¶ Create an IO block in abstract view.
Parameters: name (
str
) – Name of the IO blockKeyword Arguments: - input_only (
bool
) – If set toTrue
, the IO block is output-only - output_only (
bool
) – If set toTrue
, the IO block is input-only - **kwargs – Additional attributes to be associated with the block. Beware that these attributes are
NOT carried over to the design view automatically generated by
Translation
Returns: Return type: - input_only (
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build_logic_block
(name, width=1, height=1, **kwargs)¶ Create a logic block in abstract view.
Parameters: - name (
str
) – Name of the logic block - width (
int
) – Width of the logic block - height (
int
) – Height of the logic block
Keyword Arguments: **kwargs – Additional attributes to be associated with the block. Beware that these attributes are NOT carried over to the design view automatically generated by
Translation
Returns: Return type: - name (
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build_multimode
(name, **kwargs)¶ Create a multi-mode primitive in abstract view.
Parameters: name ( str
) – Name of the multi-mode primitiveKeyword Arguments: **kwargs – Additional attributes to be associated with the primitive Returns: Return type: MultimodeBuilder
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build_primitive
(name, *, vpr_model=None, **kwargs)¶ Create a primitive in abstract view.
Parameters: name (
str
) – Name of the primitiveKeyword Arguments: - vpr_model (
str
) – Name of the VPR model. Default: “m_{name}” - **kwargs – Additional attributes to be associated with the primitive
Returns: Return type: - vpr_model (
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build_slice
(name, **kwargs)¶ Create a slice in abstract view.
Parameters: name ( str
) – Name of the sliceKeyword Arguments: **kwargs – Additional attributes to be associated with the slice. Beware that these attributes are NOT carried over to the design view automatically generated by Translation
Returns: Return type: SliceBuilder
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build_switch_box
(corner, *, identifier=None, dont_create=False, **kwargs)¶ Get or create a switch box in abstract view at a specific corner.
Parameters: corner (
Corner
) – On which corner of a tile is the switch boxKeyword Arguments: - identifier (
str
) – If different switches boxes are needed for the same corner, use identifier to differentiate them - dont_create (
bool
) – If set toTrue
, returnNone
when the requested switch box is not already created - **kwargs – Additional attributes to be associated with the box if created. Beware that these
attributes are NOT carried over to the design view automatically generated by
Translation
Returns: Return type: - identifier (
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build_tile
(block=None, capacity=None, *, width=1, height=1, name=None, edge=OrientationTuple(north=False, east=False, south=False, west=False), disallow_segments_passthru=False, **kwargs)¶ Create a tile in abstract view.
Parameters: Keyword Arguments: - width (
int
) – Width of the tile. Overriden by the width ofblock
ifblock
is specified. - height (
int
) – Height of the tile. Overriden by the height ofblock
ifblock
is specified. - name (
str
) – Name of the tile."tile_{block}"
by default ifblock
is specified. - edge (
OrientationTuple
[bool
]) – Specify on which edges of the top-level is the tile. This affects if IO blocks can be instantiated - disallow_segments_passthru (
bool
) – If set toTrue
, routing tracks are not allowed to run over the tile - **kwargs – Additional attributes assigned to the tile
Returns: Return type: - width (
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create_global
(name, width=1, *, is_clock=False, bind_to_position=None, bind_to_subtile=None)¶ Create a global wire.
Parameters: - name (
str
) – Name of the global wire - width (
int
) – Number of bits in the global wire
Keyword Arguments: - is_clock (
bool
) – Set toTrue
if this global wire is a clock. A global clock must be 1-bit wide - bind_to_position (
Position
) – Assign the IOB at the position as the driver of this global wire. If not specified, useGlobal.bind
to bind later - bind_to_subtile (
int
) – Assign the IOB with the subtile ID as the driver of this global wire. Ifbind_to_position
is specified,bind_to_subtile
is0
by default
Returns: The created global wire
Return type: - name (
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create_memory
(addr_width, data_width, *, name=None, vpr_model=None, memory_type='1r1w', **kwargs)¶ Create a memory in abstract view.
Parameters: - addr_width (
int
) – Number of bits of the address ports - data_width (
int
) – Number of bits of the data ports
Keyword Arguments: - name (
str
) – Name of the memory module. Default: “ram_{memory_type}_a{addr_width}d{data_width}” - vpr_model (
str
) – Name of the VPR model. Default: “m_ram_{memory_type}” - memory_type (
str
) –"1r1w"
,"1rw"
or"2rw"
. Default is"1r1w"
- **kwargs – Additional attributes assigned to the primitive
Returns: Return type: - addr_width (
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create_multimode_memory
(core_addr_width, data_width, *, addr_width=None, name=None)¶ Create a multi-mode RAM.
Parameters: - core_addr_width (
int
) – The address width of the single-mode, 1R1W RAM core behind the multi-mode logic - data_width (
int
) – The data width of the single-mode, 1R1W RAM core behind the multi-mode logic
Keyword Arguments: - name (
str
) – Name of the multi-mode primitive."fracram_a{addr_width}d{data_width}"
by default. - addr_width (
int
) – The maximum address width. See notes for more information
Returns: User view of the multi-modal primitive
Return type: Notes
This method builds a multi-mode, fracturable 1R1W RAM. For example,
build_multimode_memory(ctx, 9, 64)
creates a multimode primitive with the following modes:512x64b
,1K32b
,2K16b
,4K8b
,8K4b
,16K2b
, and32K1b
.If 1b is not the desired smallest data width, change
addr_width
to a number betweencore_addr_width
andcore_addr_width + floor(log2(data_width))
.When
data_width
is not a power of 2, the actual data width of each mode is determined by the actual address width. For example,build_multimode_memory(ctx, 9, 72)
creates the following modes:512x72b
,1K36b
,2K18b
,4K9b
,8K4b
,16K2b
,32K1b
. Note that instead of a9K4b
, we got a8K4b
.- core_addr_width (
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create_multiplier
(width_a, width_b=None, *, name=None)¶ Create a basic combinational multiplier.
Parameters: - width_a (
int
) – Width of the multiplier/multiplicand - width_b (
int
) – Width of the other multiplier/multiplicand. Equal towidth_a
if not set.
Keyword Arguments: name (
str
) – Name of the primitive."mul_a{width_a}b{width_b}"
by default.Returns: User view of the multiplier
Return type: - width_a (
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create_segment
(name, width, length=1)¶ Create a segment.
Parameters: - name (
str
) – Name of the segment - width (
int
) – Number of instances of this segment per channel - length (
int
) – Length of the segment
Returns: Return type: - name (
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create_tunnel
(name, source, sink, offset)¶ Create a direct inter-block tunnel.
Parameters: - name (
str
) – Name of the tunnel - source (
Port
) – Source of the tunnel. Must be a logic block output port - sink (
Port
) – Sink of the tunnel. Must be a logic block input port - offset (
tuple
[int
,int
]) – Position of the source port relative to the sink port This definition is the opposite of how VPR defines adirect
tag. In addition,offset
is defined based on the position of the ports, not the blocks
Returns: Return type: - name (
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cwd
¶
-
database
¶ Module database.
Type: Mapping
[tuple
[ModuleView
,Hashable
],Module
]
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fasm_delegate
¶ FASM delegate for bitstream generation.
Type: FASMDelegate
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pickle
(file_)¶ Pickle the architecture context into a file.
Parameters: file ( str
or file-like object) – output file or its name
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pickle_summary
(file_)¶ Pickle the summary into a binary file.
Parameters: file ( str
or file-like object) – output file or its name
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prog_entry
¶ Programming circuitry type entry point.
Type: AbstractProgCircuitryEntry
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renderer
¶ File renderer of the current context.
Type: FileRenderer
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summary
¶
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switch_delegate
¶ Switch delegate.
This is usually set by the programming circuitry entry point, e.g.,
Scanchain
.Type: SwitchDelegate
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template_search_paths
¶
-
tunnels
¶ A mapping from names to direct inter-block tunnels.
Type: Mapping
[str
,DirectTunnel
]
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classmethod
unpickle
(file_)¶ Unpickle a pickled architecture context.
Parameters: file ( str
or file-like object) – the pickled file
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version
¶
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