prga.core.builder.block module¶
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class
prga.core.builder.block.IOBlockBuilder(context, module)¶ Bases:
prga.core.builder.block._BaseSliceLikeBuilderIO block builder.
Parameters: -
create_global(global_, orientation=None, *, name=None, **kwargs)¶ Create and add an input port that is connected to the global wire
global_.Parameters: - global (
Global) – The global wire this port is connected to - orientation (
Orientationorstr) – Orientation of this port
Keyword Arguments: - name (
str) – Name of this port. If not given, the name of the global wire is used - **kwargs – Additional attributes assigned to the port
Returns: The created port
Return type: - global (
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create_input(name, width, orientation=None, **kwargs)¶ Create and add a non-global input port to this block.
Parameters: - name (
str) – name of the created port - width (
int) – width of the created port - orientation (
Orientationorstr) – orientation of this port
Keyword Arguments: **kwargs – Additional attributes assigned to the port
Returns: The created port
Return type: - name (
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create_output(name, width, orientation=None, **kwargs)¶ Create and add a non-global output port to this block.
Parameters: - name (
str) – name of the created port - width (
int) – width of the created port - orientation (
Orientationorstr) – orientation of this port
Keyword Arguments: **kwargs – Additional attributes assigned to the port
Returns: The created port
Return type: - name (
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class
prga.core.builder.block.LogicBlockBuilder(context, module)¶ Bases:
prga.core.builder.block._BaseSliceLikeBuilderLogic block builder.
Parameters: -
classmethod
_resolve_orientation_and_position(block, orientation, position)¶ Resolve orientation and position.
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create_global(global_, orientation, position=None, *, name=None, **kwargs)¶ Create and add an input port that is connected to a global wire
global_.Parameters: - global (
Global) – The global wire this port is connected to - orientation (
Orientationorstr) – Orientation of this port - position (
tuple[int,int]) – Position of this port
Keyword Arguments: - name (
str) – Name of this port. If not given, the name of the global wire is used - **kwargs – Additional attributes assigned to the port
Returns: The created port
Return type: - global (
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create_input(name, width, orientation, position=None, *, vpr_equivalent_pins=False, **kwargs)¶ Create and add a non-global input port to this block.
Parameters: - name (
str) – name of the created port - width (
int) – width of the created port - orientation (
Orientationorstr) – orientation of this port - position (
tuple[int,int]) – Position of this port
Keyword Arguments: - vpr_equivalent_pins (
bool) – Add equivalent tag for this port in the output VPR specs - **kwargs – Additional attributes assigned to the port
Returns: The created port
Return type: - name (
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create_output(name, width, orientation, position=None, **kwargs)¶ Create and add a non-global output port to this block.
Parameters: - name (
str) – name of the created port - width (
int) – width of the created port - orientation (
Orientationorstr) – orientation of this port - position (
tuple[int,int]) – Position of this port
Keyword Arguments: **kwargs – Additional attributes assigned to the port
Returns: The created output port
Return type: - name (
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classmethod
new(name, width, height, **kwargs)¶ Create a new block for building.
Parameters: - name (
str) – Name of the block - width (
int) – Width of the block - height (
int) – Height of the block
Keyword Arguments: **kwargs – Additional attributes assigned to the block
Returns: The created block
Return type: - name (
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classmethod
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class
prga.core.builder.block.SliceBuilder(context, module)¶ Bases:
prga.core.builder.block._BaseSliceLikeBuilderSlice builder.
Parameters: -
create_clock(name, **kwargs)¶ Create and add a clock input port to the slice.
Parameters: name ( str) – Name of this clockKeyword Arguments: **kwargs – Additional attributes assigned to the port Returns: The created clock port Return type: Port
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create_input(name, width, **kwargs)¶ Create and add a non-clock input port to the slice.
Parameters: - name (
str) – Name of this port - width (
int) – Number of bits in the port
Keyword Arguments: **kwargs – Additional attributes assigned to the port
Returns: The created input port
Return type: - name (
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create_output(name, width, **kwargs)¶ Create and add a non-clock output port to the slice.
Parameters: - name (
str) – Name of this port - width (
int) – Number of bits in the port
Keyword Arguments: **kwargs – Additional attributes assigned to the port
Returns: The created output port
Return type: - name (
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class
prga.core.builder.block._BaseSliceLikeBuilder(context, module)¶ Bases:
prga.core.builder.base.BaseBuilderBase class for slice-like module builders.
Parameters: -
_set_clock(port)¶ Set
portas the clock of the module.Parameters: Port – Clock port in this module At the moment only one clock is supported in the module.
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connect(sources, sinks, *, fully=False, vpr_pack_patterns=None, **kwargs)¶ Connect
sourcestosinks.Parameters: - sources – Source nets, i.e., an input port, an output pin of an instance, a subset of the above, or a list of a combination of the above
- sinks – Sink nets, i.e., an output port, an input pin of an instance, a subset of the above, or a list of a combination of the above
Keyword Arguments: - fully (
bool) – If set toTrue, connections are made between every source and every sink - vpr_pack_patterns (
Sequence[str]) – Add pack_pattern tags to the connections - **kwargs – Additional attibutes assigned to all connections
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instantiate(model, name, reps=None, **kwargs)¶ Instantiate
modelin the module.Parameters: - model (
Module) – Abstract view of the module to be instantiated - name (
str) – Name of the instance. Ifrepsis specified, each instance is named"{name}_i{index}" - reps (
int) – If set to a positive int, the specified number of instances are created, added to the mode, and returned. This affects the num_pb attribute in the output VPR specs
Keyword Arguments: **kwargs – Additional attributes assigned to the instance(s)
Returns: Return type: - model (
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