prga.tools.util module¶
-
class
prga.tools.util.
AppIntf
(name)¶ Bases:
prga.util.Object
Interface of the application to be mapped onto the FPGA.
Parameters: name ( str
) – Name of the application-
class
AppPort
(name, direction, range_=None)¶ Bases:
prga.util.Object
Port of the application to be mapped onto the FPGA.
Parameters: - name (
str
) – Name of the port - direction (
PortDirection
orstr
) – Direction of the port - range (
slice
) – Range specifier of the port
-
direction
¶
-
get_io_constraint
(index=None)¶ Get the IO constraint assigned to this port, or a bit in this port.
Parameters: index ( int
) – Index of a bit in this port. Not applicable if this port is single-bit; Required if this port is multi-bit.Returns: Position and subtile ID of the assigned IOB Return type: Position
,int
Notes
index
respects the range specifier, i.e. ifrange_
is7:4
,index = 4
returns the last IO constraint.
-
ioconstraints
¶
-
iter_indices
()¶ Iterate through the indices of this port.
Yields: int
orNone
-
iter_io_constraints
()¶ Iterate through the indices and IO constraints of this port.
Yields: int
orNone` -- Index :obj:`tuple` [`Position`, :obj:`int`] or ``None
: Position and subtile ID of the IOB assigned for the bit in the port
-
name
¶
-
range_
¶
-
set_io_constraint
(position, subtile=0, index=None)¶ Set IO constraint to this port or a bit in this port.
Parameters: - position (
tuple
[int
,int
]) – Position of the IOB - subtile (
int
) – Subtile ID of the IOB - index (
int
) – Index of a bit in this port. Not applicable if this port is single-bit; Required if this port is multi-bit.
Notes
index
respects the range specifier, i.e. ifrange_
is7:4
,index = 4
returns the last IO constraint.- position (
-
width
¶ Width of this port.
Type: int
- name (
-
_port_reprog
= re.compile('^(?P<bus>.*)\\[(?P<index>\\d+)\\]$')¶
-
add_port
(name, direction, range_=None)¶ Add a port to this interface.
Parameters: - name (
str
) – Name of the port - direction (
PortDirection
orstr
) – Direction of the port - range (
None
) – [Overloaded] Width of the port. When using a singleint
, the port is assumed to be equivalent to Verilog{input|output} [{range_ - 1}:0] {name}
. - range – [Overloaded] Range specifier of the port.
step
must beNone
,1
or-1
. When using aslice
object, the port is equivalent to Verilog{input|output} [{range_.start}:{range_.stop - range_.step}] {name}
. Note the extrastep
caused by the difference between Python and Verilog range specification conventions (i.e.7:4
in Verilog is equivalent to7:3:-1
in Python, and2:4
in Verilog is equivalent to2:5
in Python). - range – [Overloaded] When using
None
, this port is treated as single-bit, i.e. equivalent to Verilog{input|output} {name}
.
Returns: The created port
Return type: - name (
-
name
¶
-
classmethod
parse_eblif
(f)¶ Parse a synthesized eblif file for the application interface.
Parameters: f ( str
or a file-like object) – File name, or a file-like object
-
ports
¶
-
class
-
prga.tools.util.
create_argparser
(module, *args, **kwargs)¶ Create an argument parser.
Parameters: module ( str
) – Name of the Python moduleReturns: Return type: argparse.ArgumentParser
Recommended usage:
parser = create_argparser(__name__, **kwargs)
-
prga.tools.util.
docstring_from_argparser
(parser)¶ Compile the docstring for an executable Python module from the argument parser.
Parameters: parser ( argparse.ArgumentParser
) –Returns: Return type: str
Recommended usage:
__doc__ = docstring_from_argparser(parser)