prga.netlist.net package¶
Classes for nets and net references.
Notes
- All nets/net references are sequences and can be indexed using integers to get individual bits, or using slices (range specifiers) to get consecutive subsets.
- All nets in PRGA are indexed in a big-endian fashion, so a 4-bit bus is equivalent to
wire [3:0]
in Verilog. PRGA does not support little-endian indexing so there is no way to expresswire [0:3]
as in Verilog. - When using a slice to index a net, if the
stop
value is equal to or smaller than thestart
value, the slice is treated as a Verilog-style index. That is,n[2:0]
works the same way as in Verilog and returns the lower 3 bits of netn
. On the other side, if thestop
value is larger than thestart
value, the slice is interpretted as a Python-style index, son[0:2]
returns the lower 2 bits of netn
. Note the difference in the number of bits returned. - On the contrary to indexing, iteration of nets is little-endian, i.e. starts from the LSB. So
for bit in net:
visitsn[0]
first, thenn[1]
, then so on so forth. This design decision is motivated by the fact that iteration is not really a thing in Verilog but is often used in Python, so we follow the Python convention.