prga.netlist.net.bus module¶

Port & Pin classes.

class prga.netlist.net.bus.HierarchicalPin(instance, model)¶

Bases: prga.netlist.net.common.AbstractNet

Reference to a pin of a hierarchical instance.

Parameters:	instance (`HierarchicalInstance`) – The instance that this pin belongs to model (`Port`) – The port in the model of `instance` that this pin corresponds to

_instance¶

_model¶

instance¶

The instance that this pin belongs to.

Type:	`HierarchicalInstance`

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

model¶

The port in the model of Pin.instance that this pin corresponds to.

Type:	`Port`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

class prga.netlist.net.bus.Pin(instance, model, **kwargs)¶

Bases: prga.netlist.net.bus._Bus

Pins of instances.

Keyword Arguments:
Parameters:	instance (`Instance`) – The instance that this pin belongs to model (`Port`) – The port in the model of `instance` that this pin corresponds to
	**kwargs – Custom key-value arguments. These attributes are added to `__dict__` of this object and accessible as dynamic attributes

_instance¶

_model¶

instance¶

The instance that this pin belongs to.

Type:	`Instance`

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

is_sink¶

Test if this net can be driven by other nets.

Type:	`bool`

is_source¶

Test if this net can be used as drivers of other nets.

Type:	`bool`

model¶

The port in the model of Pin.instance that this pin corresponds to.

Type:	`Port`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

class prga.netlist.net.bus.Port(parent, name, width, direction, *, is_clock=False, key=None, **kwargs)¶

Bases: prga.netlist.net.bus._Bus

Ports of modules.

Keyword Arguments:
Parameters:	parent (`Module`) – Parent module of this port name (`str`) – Name of this port width (`int`) – Width of this port direction (`PortDirection` or `str`) – Direction of the port
	is_clock (`bool`) – Set if this port is a clock key (`Hashable`) – A hashable key used to index this port in the ports mapping in the parent module. If not set (default argument: `None`), `name` is used by default **kwargs – Custom key-value arguments. These attributes are added to `__dict__` of this object and accessible as dynamic attributes

_direction¶

_is_clock¶

_key¶

_name¶

_parent¶

_width¶

direction¶

Direction of this port.

Type:	`PortDirection`

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

is_sink¶

Test if this net can be driven by other nets.

Type:	`bool`

is_source¶

Test if this net can be used as drivers of other nets.

Type:	`bool`

key¶

A hashable key to index this port in its parent module’s ports mapping.

Type:	`Hashable`

name¶

Name of this port

Type:	`str`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

class prga.netlist.net.bus._Bit(bus, index, **kwargs)¶

Bases: prga.netlist.net.common.AbstractNonReferenceNet

A single, persistent bit in a bus.

Keyword Arguments:
Parameters:	bus (`AbstractNonReferenceNet`) – The bus that this bit belongs to index (`int`) – The index of this bit in the bus
	**kwargs – Custom key-value arguments. These attributes are added to `__dict__` of this object and accessible as dynamic attributes

_bus¶

_connections¶

_index¶

bus¶

The bus that this bit belongs to.

Type:	`AbstractNonReferenceNet`

index¶

The index of this bit in the bus.

Type:	`int`

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

is_sink¶

Test if this net can be driven by other nets.

Type:	`bool`

is_source¶

Test if this net can be used as drivers of other nets.

Type:	`bool`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

class prga.netlist.net.bus._Bus(**kwargs)¶

Bases: prga.netlist.net.common.AbstractNonReferenceNet

Base class for Port and Pin.

_bits¶

_break_bits()¶

Break bus coalescence into bits. This method should only be used in NetUtils._break_bits. Beware that this method doesn’t update the connections in the _connections mapping.

Returns:	The current `_connections` value.
Return type:	`dict`
Raises:	`AttributeError` – If `_connections` is undefined, i.e. the bus is already broken into bits.

_coalesce_connections¶

_connections¶