prga.tools.wizard.verif module¶

This is an executable module:

usage: python -m prga.tools.wizard.verif [-h]: {makefile,mk,make,testbench,tb} …

PRGA verification project generator.

Auto-generate Makefile, testbench, etc. This tool depends on the Verilog-to-Bitstream project generator tool. This tool also takes a configuration file in YAML or JSON format. The configuration file requires the following keys:

compiler (string): Verilog compiler. Supported values are: "vcs", "iverilog"
tests (map of maps): Tests for the application, indexed by the name of the test
    sources (list of strings): Verilog source files of the test
    includes (list of strings): [optional] Include directories of the test
    defines (map of strings to strings, numbers or null): [optional] Define macros for Verilog preprocessing
    parameters (map of strings to strings or numbers): [optional] Parameterization of the top-level test
    comp_flags (list of strings): Additional flags for compilation
    run_flags (list of strings): Additional flags for simulation

optional arguments:

-h, --help

show this help message and exit

subcommands:

Subcommands. Run with ‘{{subcommand}} -h’ for more help

{makefile,mk,make,testbench,tb}

prga.tools.wizard.verif.generate_verif_makefile(summary, renderer, v2b_dir, config_f, config=None, test=None, output=None)¶: Generate verification makefile.

prga.tools.wizard.verif.generate_verif_testbench(renderer, v2b_dir, config, test=None, output=None)¶: Generate verification testbench.