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prga.tools.wizard.v2b module

This is an executable module:

usage: python -m prga.tools.wizard.v2b [-h] [-o OUTPUT] CONFIG.YAML

PRGA Verilog-to-Bitstream project generator.

Auto-generate Makefile, synthesis script, etc. This tool takes a configuration file in YAML or JSON format. The configuration file requires the following keys:

context (string): File name of the pickled PRGA context
app (map): Data needed to describe the application to be mapped onto the FPGA
    name (string): Name of the top-level module
    sources (list of strings): Verilog source files
    includes (list of strings): [optional] Include directories
    defines (map of strings to strings, numbers or null): [optional] Define macros for Verilog preprocessing
    parameters (map of strings to strings or numbers): [optional] Parameterization of the top-level module

The configuration file takes these optional keys:

constraints (map): Various constraints
    io (string): File name of the [partial] IO constraint

positional arguments:

CONFIG.YAML Configuration file in YAML or JSON format

optional arguments:

-h, --help	show this help message and exit
-o OUTPUT, --output OUTPUT
	Output directory. All files are generated into the current directory by default

prga.tools.wizard.v2b.generate_v2b_project(context, renderer, config, output=None)

Generate Verilog-to-Bitstream project.

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