prga.netlist.net.common module¶

Common enums and abstract base class for nets.

class prga.netlist.net.common.AbstractNet¶

Bases: prga.util.Object, collections.abc.Sequence

Abstract class for all nets and net references.

_auto_index(index)¶

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

net_type¶

Type of the net.

Type:	`NetType`

class prga.netlist.net.common.AbstractNonReferenceNet¶

Bases: prga.netlist.net.common.AbstractNet

Abstract class for all non-reference nets.

is_sink¶

Test if this net can be driven by other nets.

Type:	`bool`

is_source¶

Test if this net can be used as drivers of other nets.

Type:	`bool`

parent¶

Parent module of this net.

Type:	`Module`

class prga.netlist.net.common.Concat(items)¶

Bases: prga.netlist.net.common.AbstractNet

A concatenation of slices and/or buses.

Parameters:	items (`Sequence` [`AbstractNet` ]) – Items to be contenated together

Direct instantiation of this class is not recommended. Use NetUtils.concat instead.

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

items¶

net_type¶

Type of the net.

Type:	`NetType`

class prga.netlist.net.common.Const(value=None, width=None)¶

Bases: prga.netlist.net.common.AbstractNonReferenceNet

Constant-value nets used as tie-high/low or unconnected status marker for sinks.

Parameters:	value (`int`) – Value of this constant. Use `None` to represent “unconnected” width (`int`) – Number of bits in this net

_Const__singletons = {}¶

_value¶

_width¶

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

is_sink¶

Test if this net can be driven by other nets.

Type:	`bool`

is_source¶

Test if this net can be used as drivers of other nets.

Type:	`bool`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

value¶

Value of this constant net.

Type:	`int`

class prga.netlist.net.common.NetType¶

Bases: prga.util.Enum

Enum type for nets and net references.

bit = 3¶: one single bit in a bus

concat = 6¶: concatenations of buses and/or subsets

const = 0¶: constant-value nets

hierarchical = 4¶: hierarchical pin buses

is_reference¶

Test if this type is a reference.

Type:	`bool`

pin = 2¶: pin (input/output of an instance in a module) buses

port = 1¶: port (input/output of a module) buses

slice_ = 5¶: consecutive subsets (slices) of a bus

class prga.netlist.net.common.PortDirection¶

Bases: prga.util.Enum

Enum type for port/pin directions.

input_ = 0¶: input direction

opposite¶

The opposite of the this direction.

Returns:	the enum value of the opposite direction.
Return type:	`PortDirection`

output = 1¶: output direction

class prga.netlist.net.common.Slice(bus, range_)¶

Bases: prga.netlist.net.common.AbstractNet

Reference to a consecutive subset of a bus.

Parameters:	bus (`AbstractNet`) – The referenced bus range (`slice`) – Range of the bit(s) in the bus.

Do not directly instantiate this class. Index into the bus instead, e.g. module.ports[0:4]

bus¶

index¶

Index of the bit in the bus. Only valid when this object is a bit reference, i.e. length equals to 1.

Type:	`int`

is_clock¶

Test if this net is part of a clock network.

Type:	`bool`

net_type¶

Type of the net.

Type:	`NetType`

parent¶

Parent module of this net.

Type:	`Module`

range_¶

class prga.netlist.net.common.TimingArcType¶

Bases: prga.util.Enum

Timing arc types.

comb_bitwise = 0¶: combinational propagation delay of a bitwise timing arc

comb_matrix = 1¶: combinational propagation delay of an all-to-all timing arc

seq_end = 3¶: clock -> sequential endpoint(s), i.e., setup & hold

seq_start = 2¶: clock -> sequential startpoint(s), i.e., clk2q