Table Of Contents
Table Of Contents

prga.prog.frame.lib module

class prga.prog.frame.lib.Frame

Bases: prga.prog.common.AbstractProgCircuitryEntry

Entry point for frame programming circuitry.

class _FrameDecoderTreeLeaf(instance)

Bases: prga.util.Object

addr_width
instance
is_leaf
class _FrameDecoderTreeNode(first_child, parent=None)

Bases: prga.util.Object

add_node(node)
addr_width
child_addr_width
children
is_leaf
parent
classmethod _Frame__install_cells(context)
classmethod _construct_decoder_tree(context, module, nets, node, *, _treenets=None, baseaddr=0)
classmethod _get_or_create_frame_buffer(context, data_width)
classmethod _get_or_create_frame_data_cell(context, data_width)
classmethod _get_or_create_frame_prog_nets(module, word_width, addr_width, excludes=None)
classmethod _get_or_create_frame_rbmerge(context, num_sources, num_stages)
classmethod _get_or_create_frame_wldec(context, addr_width, num_sinks)
classmethod _insert_frame_array(context, *, dmod=None, _visited=None)

Insert frame-based programming circuitry hierarchically.

Parameters:

context (Context) –

Keyword Arguments:
 
  • dmod (Module) – Design-view of the array in which programming circuitry is to be inserted
  • _visited (dict [Hashable, int ]) – Mapping from module keys to levels of buffering inside that module. Blocks and routing boxes, i.e. leaf-level modules, are buffered for one level. That is, a read access returns after three cycles (1 cycle request buffering, 1 cycle read, 1 cycle read-back merging)
Returns:

Levels of buffering in dmod
Return type:

int
classmethod _insert_frame_leaf(context, dmod, visited, *, _not_top=False)

Insert frame-based programming circuitry into logic/io blocks and switch/connection boxes.

Returns:addr_width needed for this leaf
Return type:int
classmethod _insert_frame_tile(context, dmod)

Insert frame-based programming circuitry hierarchically.

Parameters:
  • context (Context) –
  • dmod (Module) – Design-view of the tile in which programming circuitry is to be inserted
  • _visited (dict [Hashable, int ]) – Mapping from module keys to levels of buffering inside that module. Blocks and routing boxes, i.e. leaf-level modules, are buffered for one level. That is, a read access returns after three cycles (1 cycle request buffering, 1 cycle read, 1 cycle read-back merging)
classmethod _instantiate_buffer(context, module, nets, addr_width, *, suffix='')
classmethod _instantiate_decoder(context, module, nets, subnets, addrnet, *, suffix='', merger_stage=1, dont_connect_subnets=False)
classmethod _traverse_and_insert_leaves(context, *, dmod=None, _visited=None)
classmethod insert_prog_circuitry(context)

Insert programming circuitry into the FPGA. This method will be called by the ProgCircuitryInsertion pass.

Parameters:context (Context) –
classmethod materialize(ctx, inplace=False, *, word_width=1)

Materialize the abstract context to this configuration circuitry type.

Parameters:
  • ctx (Context) – An abstract context, or a context previously materialized to another configuration circuitry type.
  • inplace (bool) – If set, the context is modified in-place. Otherwise (by default), ctx is deep-copied before processed
Keyword Arguments:
 

**kwargs – Additional keyword parameters specific to the programming circuitry type.
Returns:
Return type:

Context
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