prga.passes.vpr.rrg module¶

class prga.passes.vpr.rrg.VPR_RRG_Generation(output_file, *, fasm=None)¶

Generate VPR’s routing resource graph XML.

Keyword Arguments:
Parameters:	output_file (`str` of file-like object) – The output file. If the file name ends with “.gz”, the output file will be compressed using gzip
	fasm (`FASMDelegate`) – Overwrite the deafult fasm delegate provided by the context

_analyze_blockpin(pin)¶

Analyze a block pin node.

Parameters:	pin (`Pin`) – Hierarchical pin
Returns:	Position of the routing channel orientation (`Orientation`): Orientation of the port block_position (`Position`): Position of the parent block instance, used to calculate the xlow/ylow/xhigh/yhigh attributes for the src/sink nodes
Return type:	channel_position (`Position`)

_analyze_track(node)¶

Analyze a track node.

Parameters:	node (`Sequence` [`Hashable` ]) – A reference node of a switch box pin (coalesced)
Returns:	Expansion orientation lower_position (`Position`): The lower position of starting/ending channel higher_position (`Position`): The higher position of starting/ending channel ptc_position (`int`): Used to calculate the PTC for VPR
Return type:	orientation (`Orientation`)

_edge(src_id, sink_id, head_pin_bit=None, tail_pin_bit=None, delay=0.0, fasm_features=(), switch_id=None)¶

_edge_box_input(head_pin_bit, tail_pin_bit, tail_pkg, fasm_features=(), delay=0.0)¶

_edge_box_output(head_pin_bit, tail_pin_bit, tail_pkg, fasm_features=(), delay=0.0)¶

_node(type_, id_, ptc, xlow, ylow, *, track_dir=None, port_ori=None, xhigh=None, yhigh=None, segment=None, capacity=1)¶

is_readonly_pass¶

Test if this is a read-only pass that can be run multiple times.

Type:	`bool`

run(context)¶

Run the pass.

Parameters:	context (`Context`) – The context which manages all architecture data