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prga.passes.rtl module

class prga.passes.rtl.VerilogCollection(src_output_dir='.', header_output_dir=None, view=<ModuleView.design: 1>, incremental=False)

Bases: prga.passes.base.AbstractPass

Collecting Verilog rendering tasks.

Parameters:

src_output_dir (str) – Verilog source files are generated in the specified directory. Default value is the current working directory.

Keyword Arguments:  

• header_output_dir (str) – Verilog header files are generated in the specified directory. Default value is “{src_output_dir}/include”
• view (ModuleView or str) – Generate Verilog source files with the specified view
• incremental (bool) – If set to True, the RTL sources already listed in context.summary.rtl["sources"] will not be overwritten

_process_header(context, h, requirer)

_process_module(context, module)

added_headers

dependences

Passes that this pass depend on.

header_output_dir

incremental

is_readonly_pass

Test if this is a read-only pass that can be run multiple times.

Type:bool

key

Key of this pass.

renderer

run(context)

Run the pass.

Parameters:context (Context) – The context which manages all architecture data

src_output_dir

view

visited_modules

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