prga.core.common module¶

Common enums for FPGA builders.

class prga.core.common.AbstractRoutingNodeID¶

Bases: prga.util.Object, collections.abc.Hashable

Abstract base class for routing node IDs.

node_type¶

Type of this node (block, segment or bridge).

Type:	`NetClass`

position¶

Anchor position of this node ID.

Type:	`Position`

prototype¶

Prototype of this routing node ID.

Type:	`Port` or `Segment`

class prga.core.common.BlockFCValue¶

Bases: prga.core.common.BlockFCValue

A named tuple used for defining FC values for a specific block.

Parameters:	default_in (`int`, `float`, or `BlockPortFCValue`) – the default FC value for all input ports default_out (`int`, `float`, or `BlockPortFCValue`) – the default FC value for all output ports. Same as the default value for input ports if not set overrides (`Mapping` [`str`, `int` or `float` or `BlockPortFCValue` ]) – the FC value for a specific port

classmethod _construct(*args)¶: Quick construction of a BlockFCValue.

port_fc(port, segment, all_sections=False)¶

Get the FC value for a specific port and a specific segment.

Parameters:	port (`Port`) – segment (`Segment`) – all_sections (`bool`) – if all sections of a segment longer than 1 should be taken into consideration
Returns:	Number of tracks connected per port bit
Return type:	`int`

class prga.core.common.BlockPinID¶

Bases: prga.core.common.BlockPinID, prga.core.common.AbstractRoutingNodeID

ID of block pin nodes.

Parameters:	position (`tuple` [`int`, `int` ]) – anchor position prototype (`Port`) – subtile (`int`) – subtile ID in a tile

move(offset)¶

Create a new BlockPinID with the specified adjustment to the position of this ID.

Parameters:	offset (`tuple` [`int`, `int` ]) –
Returns:
Return type:	`BlockPinID`

node_type¶

Type of this node (block, segment or bridge).

Type:	`NetClass`

class prga.core.common.BlockPortFCValue¶

Bases: prga.core.common.BlockPortFCValue

A named tuple used for defining FC values for a specific block port.

Parameters:	default (`int` or `float`) – the default FC value for this port overrides (`Mapping` [`str`, `int` or `float` ]) – the FC value for a specific segment type

classmethod _construct(*args)¶: Quick construction of a BlockPortFCValue.

default¶

Default FC value for this block port.

Type:	`int` or `float`

overrides¶

the FC value for a specific segment type.

Type:	`Mapping` [`str`, `int` or `float` ])

segment_fc(segment, all_sections=False)¶

Get the FC value for a specific segment.

Parameters:	segment (`Segment`) – all_sections (`bool`) – if all sections of a segment longer than 1 should be taken into consideration
Returns:	Number of tracks connected per port bit
Return type:	`int`

class prga.core.common.BridgeID¶

Bases: prga.core.common.BridgeID, prga.core.common.AbstractRoutingNodeID

ID of bridges.

Parameters:	position (`tuple` [`int`, `int` ]) – anchor position prototype (`Segment`) – orientation (`Orientation`) – orientation bridge_type (`BridgeType`) – type of the bridge

convert(bridge_type=None)¶

Convert to a segment ID or bridge ID.

Parameters:	bridge_type (`BridgeType`) – Convert to a `BridgeID` of the specified type, or a `SegmentID` if not specified
Returns:	`SegmentID` if `bridge_type` is not specified; Otherwise `BridgeID`

move(offset)¶

Create a new BridgeID with the specified adjustment to the position of this bridge ID.

Parameters:	offset (`tuple` [`int`, `int` ]) –
Returns:
Return type:	`BridgeID`

node_type¶

Type of this node (block, segment or bridge).

Type:	`NetClass`

class prga.core.common.BridgeType¶

Bases: prga.util.Enum

Bridge types.

cboxout = 2¶: cboxout-sboxin

cboxout2 = 3¶: secondary cboxout-sboxin

regular_input = 0¶: regular segment input

regular_output = 1¶: regular segment output

class prga.core.common.Corner¶

Bases: prga.util.Enum

Corner in a 2D grid.

compose = <bound method Corner.compose of <enum 'Corner'>>¶

decompose()¶: tuple [Orientation, Orientation ]: Decompose this corner into two Orientation s. X-dimension first.

dotx(dim)¶: Direction: Direction in Dimension dim.

northeast = 0¶: Orientation.north x Orientation.east

northwest = 1¶: Orientation.north x Orientation.west

opposite¶

The opposite corner of this corner.

Type:	`Corner`

southeast = 2¶: Orientation.south x Orientation.east

southwest = 3¶: Orientation.south x Orientation.west

class prga.core.common.Dimension¶

Bases: prga.util.Enum

Segment/connection block dimensions.

perpendicular¶

The perpendicular dimension of this dimension.

Type:	`Dimension`

x = 0¶: X-dimension

y = 1¶: Y-dimension

class prga.core.common.DirectTunnel¶

Bases: prga.core.common.DirectTunnel

Direct inter-block tunnels.

Parameters:

name (str) – Name of the inter-block tunnel
source (Port) – Source of the tunnel. Must be a logic block output port
sink (Port) – Sink of the tunnel. Must be a logic block input port
offset (Position) – Position of the source port relative to the sink port This definition is the opposite of how VPR defines a direct tag. In addition, offset is defined based on the position of the ports, not the blocks

class prga.core.common.Direction¶

Bases: prga.util.Enum

Segment/relative directions.

dec = 1¶: decreasing direction

inc = 0¶: increasing direction

opposite¶

The opposite direction.

Type:	`Direction`

class prga.core.common.Global(name, width=1, is_clock=False)¶

Bases: prga.util.Object

Defining a global wire.

Parameters:	name (`str`) – Name of this global wire width (`int`) – Number of bits of this global wire is_clock (`bool`) – If the global wire is a clock wire

_bound_to_position¶

_bound_to_subtile¶

_is_clock¶

_name¶

_width¶

bind(position, subtile)¶

Bind the global wire to the subtile-th IO block at position.

Parameters:	position (`tuple` [`int`, `int` ]) – subtile (`int`) –

bound_to_position¶

The position of the tile in which the global wire is bound to.

Type:	`Position` or `None`

bound_to_subtile¶

The IO block that the global wire is bound to.

Type:	`int` or `None`

is_bound¶

Test if this global wire is already bound to a specific IOB.

Type:	`bool`

is_clock¶

Test if this global wire is a clock wire.

Type:	`bool`

name¶

Name of this global wire.

Type:	`str`

width¶

Number of bits of this global wire.

Type:	`int`

class prga.core.common.IO(directions, position, subtile=0, global_=None, **kwargs)¶

Bases: prga.util.Object

One IO pad.

Keyword Arguments:
Parameters:	directions (`PortDirection` or `Sequence` [`PortDirection` ]) – One or more `PortDirection` that this IO supports position (`tuple` [`int`, `int` ]) – Position of this IO subtile (`int`) – Sub-tile ID global (`Global`) – If set, this IO drives the specified global wire
	**kwargs – Additional attributes assigned to the IO pad

directions¶

global_¶

position¶

subtile¶

class prga.core.common.IOType¶

Bases: prga.util.Enum

Types of top-level IOs.

ipin = 0¶: input

oe = 2¶: output enable

opin = 1¶: output

opposite¶

Opposite type of the IO.

Type:	`IOType`

class prga.core.common.ModuleClass¶

Bases: prga.util.Enum

Class for modules.

array = 8¶: array (containing tiles, arrays and switch boxes)

aux = 11¶: auxiliary modules

connection_box = 6¶: connection box

io_block = 3¶: IO block

is_block¶

Test if this module is a block.

Type:	`bool`

is_routing_box¶

Test if this module is a routing box.

Type:	`bool`

logic_block = 4¶: logic block

mode = 2¶: one logical mode of a multi-mode primitive

primitive = 0¶: user available primitive cells

prog = 10¶: programming modules

slice_ = 1¶: slices

switch = 9¶: switch

switch_box = 5¶: switch box

tile = 7¶: tile (containing blocks and connection boxes)

class prga.core.common.ModuleView¶

Bases: prga.util.Enum

A specific view of a module.

Currently PRGA only uses the abstract view and the design view.

abstract = 0¶: abstract view of a module

design = 1¶: design view of a module

physical = 2¶: physical view of a module

class prga.core.common.NetClass¶

Bases: prga.util.Enum

Class for nets.

block = 1¶: block ports

bridge = 3¶: bridges between blocks, boxes and arrays

global_ = 5¶: global nets

io = 4¶: chip-level inputs/outputs

prog = 7¶: programming ports

segment = 2¶: segment driver

switch = 6¶: switch input/outputs

user = 0¶: input/outputs of user-visible modules (e.g. primitive, mode, slice)

class prga.core.common.Orientation¶

Bases: prga.util.Enum

Orientation in a 2D grid.

compose = <bound method Orientation.compose of <enum 'Orientation'>>¶

decompose()¶

Decompose this orientation into dimension and direcion.

Returns:	`Direction`:
Return type:	`Dimension`

dimension¶

The dimension of this orientation.

Type:	`Dimension`

direction¶

The direction of this orientation.

Type:	`Direction`

east = 1¶: Direction.inc x Dimension.x

north = 0¶: Direction.inc x Dimension.y

opposite¶

The opposite orientation of this orientation.

Type:	`Orientation`

south = 2¶: Direction.dec x Dimension.y

west = 3¶: Direction.dec x Dimension.x

class prga.core.common.OrientationTuple¶

Bases: prga.core.common.OrientationTuple

A tuple of values, one for each orientation.

Keyword Arguments:
Parameters:	default – Default value for all orientations if no override is provided
	north – Value for the north orientation east – Value for the east orientation south – Value for the south orientation west – Value for the west orientation

Notes

The specific value of an orientation can be accessed simply by indexing this tuple with that orientation enum. For example: t = OrientationTuple(False); print(t[Orientation.north])

class prga.core.common.Position¶

Bases: prga.core.common.Position

A tuple speiciying a position in a 2D array.

Parameters:	x (`int`) – The X-dimensional position y (`int`) – The Y-dimensional position

class prga.core.common.PrimitiveClass¶

Bases: prga.util.Enum

Enum types for VPR’s class attribute of leaf pb_type .

blackbox_memory = 7¶: black-boxed memory

custom = 5¶: user-defined primitives

flipflop = 1¶: D-flipflop

inpad = 2¶: input pad

lut = 0¶: look-up table

memory = 4¶: user-defined memory

multimode = 6¶: user-defined multi-mode primitives

outpad = 3¶: output pad

class prga.core.common.PrimitivePortClass¶

Bases: prga.util.Enum

Enum types for VPR’s port_class attribute of leaf ports.

D = 3¶: flipflop data input

Q = 4¶: flipflop data output

address = 5¶: address input for single-port memory

address1 = 9¶: 1st address input for dual-port memory

address2 = 13¶: 2nd address input for dual-port memory

clock = 0¶: clock for flipflop and memory

data_in = 7¶: data input for single-port memory

data_in1 = 11¶: 2st data input for dual-port memory

data_in2 = 15¶: 2nd data input for dual-port memory

data_out = 8¶: data output for single-port memory

data_out1 = 12¶: 1st data output for dual-port memory

data_out2 = 16¶: 2nd data output for dual-port memory

lut_in = 1¶: lut input

lut_out = 2¶: lut output

write_en = 6¶: write enable for single-port memory

write_en1 = 10¶: 1st write enable for single-port memory

write_en2 = 14¶: 2nd write enable for single-port memory

class prga.core.common.Segment¶

Bases: prga.core.common.Segment

Defining a segment prototype.

Parameters:	name (`str`) – Name of this segment width (`int`) – Number of wire segments originated from one tile to one orientation length (`int`) – Length of this segment

class prga.core.common.SegmentID¶

Bases: prga.core.common.SegmentID, prga.core.common.AbstractRoutingNodeID

ID of segments.

Parameters:	position (`tuple` [`int`, `int` ]) – anchor position prototype (`Segment`) – orientation (`Orientation`) – orientation

convert(bridge_type=None)¶

Convert to a segment ID or bridge ID.

Parameters:	bridge_type (`BridgeType`) – Convert to a `BridgeID` of the specified type, or a `SegmentID` if not specified
Returns:	`SegmentID` if `bridge_type` is not specified; Otherwise `BridgeID`

move(offset)¶

Create a new SegmentID with the specified adjustment to the position of this segment ID.

Parameters:	offset (`tuple` [`int`, `int` ]) –
Returns:
Return type:	`SegmentID`

node_type¶

Type of this node (block, segment or bridge).

Type:	`NetClass`

class prga.core.common.SwitchBoxPattern¶

Bases: prga.util.Object

Switch box patterns.

class _cycle_free(fill_corners=<enum 'Corner'>)¶: Bases: prga.core.common._pattern

class _pattern(fill_corners=<enum 'Corner'>)¶

Bases: prga.util.Object

_fill_corners¶

fill_corners¶

class _span_limited(fill_corners=<enum 'Corner'>, max_span=None)¶

Bases: prga.core.common._pattern

_max_span¶

max_span¶

class _subset(fill_corners=<enum 'Corner'>)¶: Bases: prga.core.common._pattern

class _turn_limited(fill_corners=<enum 'Corner'>, max_turn=None)¶

Bases: prga.core.common._pattern

_max_turn¶

max_turn¶

class _universal(fill_corners=<enum 'Corner'>)¶: Bases: prga.core.common._pattern

class _wilton(fill_corners=<enum 'Corner'>)¶: Bases: prga.core.common._pattern

cycle_free = <prga.core.common.SwitchBoxPattern._cycle_free object>¶

span_limited = <prga.core.common.SwitchBoxPattern._span_limited object>¶

subset = <prga.core.common.SwitchBoxPattern._subset object>¶

turn_limited = <prga.core.common.SwitchBoxPattern._turn_limited object>¶

universal = <prga.core.common.SwitchBoxPattern._universal object>¶

wilton = <prga.core.common.SwitchBoxPattern._wilton object>¶